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   <div id="projectname">CMSIS-CORE
   &#160;<span id="projectnumber">Version 3.01</span>
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   <div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
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<p>Structure type to access the System Control Block (SCB).  
</p>
<table class="memberdecls">
<tr><td colspan="2"><h2><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__I uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#afa7a9ee34dfa1da0b60b4525da285032">CPUID</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x000 (R/ ) CPUID Base Register.  <a href="#afa7a9ee34dfa1da0b60b4525da285032"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#a3e66570ab689d28aebefa7e84e85dc4a">ICSR</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x004 (R/W) Interrupt Control and State Register.  <a href="#a3e66570ab689d28aebefa7e84e85dc4a"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#a0faf96f964931cadfb71cfa54e051f6f">VTOR</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x008 (R/W) Vector Table Offset Register.  <a href="#a0faf96f964931cadfb71cfa54e051f6f"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#a6ed3c9064013343ea9fd0a73a734f29d">AIRCR</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x00C (R/W) Application Interrupt and Reset Control Register.  <a href="#a6ed3c9064013343ea9fd0a73a734f29d"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#abfad14e7b4534d73d329819625d77a16">SCR</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x010 (R/W) System Control Register.  <a href="#abfad14e7b4534d73d329819625d77a16"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#a6d273c6b90bad15c91dfbbad0f6e92d8">CCR</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x014 (R/W) Configuration Control Register.  <a href="#a6d273c6b90bad15c91dfbbad0f6e92d8"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#af6336103f8be0cab29de51daed5a65f4">SHP</a> [12]</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15)  <a href="#af6336103f8be0cab29de51daed5a65f4"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#ae9891a59abbe51b0b2067ca507ca212f">SHCSR</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x024 (R/W) System Handler Control and State Register.  <a href="#ae9891a59abbe51b0b2067ca507ca212f"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#a2f94bf549b16fdeb172352e22309e3c4">CFSR</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x028 (R/W) Configurable Fault Status Register.  <a href="#a2f94bf549b16fdeb172352e22309e3c4"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#a7bed53391da4f66d8a2a236a839d4c3d">HFSR</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x02C (R/W) HardFault Status Register.  <a href="#a7bed53391da4f66d8a2a236a839d4c3d"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#ad7d61d9525fa9162579c3da0b87bff8d">DFSR</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x030 (R/W) Debug Fault Status Register.  <a href="#ad7d61d9525fa9162579c3da0b87bff8d"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#ac49b24b3f222508464f111772f2c44dd">MMFAR</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x034 (R/W) MemManage Fault Address Register.  <a href="#ac49b24b3f222508464f111772f2c44dd"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#a31f79afe86c949c9862e7d5fce077c3a">BFAR</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x038 (R/W) BusFault Address Register.  <a href="#a31f79afe86c949c9862e7d5fce077c3a"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#aeb77053c84f49c261ab5b8374e8958ef">AFSR</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x03C (R/W) Auxiliary Fault Status Register.  <a href="#aeb77053c84f49c261ab5b8374e8958ef"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__I uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#a3f51c43f952f3799951d0c54e76b0cb7">PFR</a> [2]</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x040 (R/ ) Processor Feature Register.  <a href="#a3f51c43f952f3799951d0c54e76b0cb7"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__I uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#a586a5225467262b378c0f231ccc77f86">DFR</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x048 (R/ ) Debug Feature Register.  <a href="#a586a5225467262b378c0f231ccc77f86"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__I uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#aaedf846e435ed05c68784b40d3db2bf2">ADR</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x04C (R/ ) Auxiliary Feature Register.  <a href="#aaedf846e435ed05c68784b40d3db2bf2"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__I uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#aec2f8283d2737c6897188568a4214976">MMFR</a> [4]</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x050 (R/ ) Memory Model Feature Register.  <a href="#aec2f8283d2737c6897188568a4214976"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__I uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#acee8e458f054aac964268f4fe647ea4f">ISAR</a> [5]</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x060 (R/ ) Instruction Set Attributes Register.  <a href="#acee8e458f054aac964268f4fe647ea4f"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#ac89a5d9901e3748d22a7090bfca2bee6">RESERVED0</a> [5]</td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserved.  <a href="#ac89a5d9901e3748d22a7090bfca2bee6"></a><br/></td></tr>
<tr><td class="memItemLeft" align="right" valign="top">__IO uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_s_c_b___type.html#af460b56ce524a8e3534173f0aee78e85">CPACR</a></td></tr>
<tr><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x088 (R/W) Coprocessor Access Control Register.  <a href="#af460b56ce524a8e3534173f0aee78e85"></a><br/></td></tr>
</table>
<hr/><h2>Field Documentation</h2>
<a class="anchor" id="aaedf846e435ed05c68784b40d3db2bf2"></a><!-- doxytag: member="SCB_Type::ADR" ref="aaedf846e435ed05c68784b40d3db2bf2" args="" -->
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          <td class="memname">__I uint32_t <a class="el" href="struct_s_c_b___type.html#aaedf846e435ed05c68784b40d3db2bf2">SCB_Type::ADR</a></td>
        </tr>
      </table>
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<a class="anchor" id="aeb77053c84f49c261ab5b8374e8958ef"></a><!-- doxytag: member="SCB_Type::AFSR" ref="aeb77053c84f49c261ab5b8374e8958ef" args="" -->
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          <td class="memname">__IO uint32_t <a class="el" href="struct_s_c_b___type.html#aeb77053c84f49c261ab5b8374e8958ef">SCB_Type::AFSR</a></td>
        </tr>
      </table>
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<a class="anchor" id="a6ed3c9064013343ea9fd0a73a734f29d"></a><!-- doxytag: member="SCB_Type::AIRCR" ref="a6ed3c9064013343ea9fd0a73a734f29d" args="" -->
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          <td class="memname">__IO uint32_t <a class="el" href="struct_s_c_b___type.html#a6ed3c9064013343ea9fd0a73a734f29d">SCB_Type::AIRCR</a></td>
        </tr>
      </table>
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</div>
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<a class="anchor" id="a31f79afe86c949c9862e7d5fce077c3a"></a><!-- doxytag: member="SCB_Type::BFAR" ref="a31f79afe86c949c9862e7d5fce077c3a" args="" -->
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          <td class="memname">__IO uint32_t <a class="el" href="struct_s_c_b___type.html#a31f79afe86c949c9862e7d5fce077c3a">SCB_Type::BFAR</a></td>
        </tr>
      </table>
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<a class="anchor" id="a6d273c6b90bad15c91dfbbad0f6e92d8"></a><!-- doxytag: member="SCB_Type::CCR" ref="a6d273c6b90bad15c91dfbbad0f6e92d8" args="" -->
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          <td class="memname">__IO uint32_t <a class="el" href="struct_s_c_b___type.html#a6d273c6b90bad15c91dfbbad0f6e92d8">SCB_Type::CCR</a></td>
        </tr>
      </table>
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<a class="anchor" id="a2f94bf549b16fdeb172352e22309e3c4"></a><!-- doxytag: member="SCB_Type::CFSR" ref="a2f94bf549b16fdeb172352e22309e3c4" args="" -->
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          <td class="memname">__IO uint32_t <a class="el" href="struct_s_c_b___type.html#a2f94bf549b16fdeb172352e22309e3c4">SCB_Type::CFSR</a></td>
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      </table>
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<a class="anchor" id="af460b56ce524a8e3534173f0aee78e85"></a><!-- doxytag: member="SCB_Type::CPACR" ref="af460b56ce524a8e3534173f0aee78e85" args="" -->
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          <td class="memname">__IO uint32_t <a class="el" href="struct_s_c_b___type.html#af460b56ce524a8e3534173f0aee78e85">SCB_Type::CPACR</a></td>
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      </table>
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<a class="anchor" id="afa7a9ee34dfa1da0b60b4525da285032"></a><!-- doxytag: member="SCB_Type::CPUID" ref="afa7a9ee34dfa1da0b60b4525da285032" args="" -->
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          <td class="memname">__I uint32_t <a class="el" href="struct_s_c_b___type.html#afa7a9ee34dfa1da0b60b4525da285032">SCB_Type::CPUID</a></td>
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<a class="anchor" id="a586a5225467262b378c0f231ccc77f86"></a><!-- doxytag: member="SCB_Type::DFR" ref="a586a5225467262b378c0f231ccc77f86" args="" -->
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          <td class="memname">__I uint32_t <a class="el" href="struct_s_c_b___type.html#a586a5225467262b378c0f231ccc77f86">SCB_Type::DFR</a></td>
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<a class="anchor" id="ad7d61d9525fa9162579c3da0b87bff8d"></a><!-- doxytag: member="SCB_Type::DFSR" ref="ad7d61d9525fa9162579c3da0b87bff8d" args="" -->
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          <td class="memname">__IO uint32_t <a class="el" href="struct_s_c_b___type.html#ad7d61d9525fa9162579c3da0b87bff8d">SCB_Type::DFSR</a></td>
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<a class="anchor" id="a7bed53391da4f66d8a2a236a839d4c3d"></a><!-- doxytag: member="SCB_Type::HFSR" ref="a7bed53391da4f66d8a2a236a839d4c3d" args="" -->
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          <td class="memname">__IO uint32_t <a class="el" href="struct_s_c_b___type.html#a7bed53391da4f66d8a2a236a839d4c3d">SCB_Type::HFSR</a></td>
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<a class="anchor" id="a3e66570ab689d28aebefa7e84e85dc4a"></a><!-- doxytag: member="SCB_Type::ICSR" ref="a3e66570ab689d28aebefa7e84e85dc4a" args="" -->
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          <td class="memname">__IO uint32_t <a class="el" href="struct_s_c_b___type.html#a3e66570ab689d28aebefa7e84e85dc4a">SCB_Type::ICSR</a></td>
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<a class="anchor" id="acee8e458f054aac964268f4fe647ea4f"></a><!-- doxytag: member="SCB_Type::ISAR" ref="acee8e458f054aac964268f4fe647ea4f" args="[5]" -->
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          <td class="memname">__I uint32_t <a class="el" href="struct_s_c_b___type.html#acee8e458f054aac964268f4fe647ea4f">SCB_Type::ISAR</a>[5]</td>
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<a class="anchor" id="ac49b24b3f222508464f111772f2c44dd"></a><!-- doxytag: member="SCB_Type::MMFAR" ref="ac49b24b3f222508464f111772f2c44dd" args="" -->
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          <td class="memname">__IO uint32_t <a class="el" href="struct_s_c_b___type.html#ac49b24b3f222508464f111772f2c44dd">SCB_Type::MMFAR</a></td>
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